New RISC-V port (#281)

* Add RISC-V support

This patch adds support for the RISC-V architecture (https://riscv.org).

This patch has been tested using QEMU user-mode emulation and GCC 7.2.0
in the following configurations:

* -march=rv32imac -mabi=ilp32
* -march=rv32g -mabi=ilp32d
* -march=rv64imac -mabi=lp64
* -march=rv64g -mabi=lp64d

The ABI currently can be found at
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md .

* Add RISC-V to README

* RISC-V: fix configure.host
This commit is contained in:
Stef O'Rear
2018-03-11 05:55:15 -07:00
committed by Anthony Green
parent dca52b55bc
commit 3840d49aaa
7 changed files with 739 additions and 0 deletions

View File

@@ -206,6 +206,11 @@ case "${host}" in
TARGET=POWERPC; TARGETDIR=powerpc
;;
riscv*-*)
TARGET=RISCV; TARGETDIR=riscv
SOURCES="ffi.c sysv.S"
;;
s390-*-* | s390x-*-*)
TARGET=S390; TARGETDIR=s390
SOURCES="ffi.c sysv.S"